Factor Analysis on Forward Voltage Rejection

Background of the Experiment
Basic electrical test for White Light Emitting Diodes ( LEDs and here termed as 'device' ) include the tests for the device's operating properties:
  • Luminosity ( Brightness )
  • Chromaticity ( Nearness to the Color of White )
  • Reverse Current ( IR )
  • Forward Voltage ( VF )
Failure of the device to pass the Forward Voltage (VF) tests is the defect the team is working on to control and reduce.

Test for VF is composed of several levels. At each level, the test condition tightens by narrowed tests limits and increased forcing time, so to ensure the stability of the device when already in use. With this program of testing, the device would usually pass the first level of test (VF1), but would fail on the second level (VF2) of the test.

The chip is suspected to be the primary factor causing the device to fail under the VF2 test condition. This is based on the idea that a production lot of chips can have a forward voltage distribution with a mean of very low bias ( i.e. very near the ideal value ), yet the dispersion is too wide that the side tails of the distribution extend beyond the VF2 test limit.

Objective of the Experiment
This experiment aims to develope and test a method of estimating the quantity of chips in a production lot,  that will have VF readings beyond VF2 test limits. The method will make VF2 occurence predictable and will become groundworks for further corrective and preventive actions for both the company and the chip makers.

Methodology
Each lot of chips comes with statistical parameters ( mean, standard deviation, maximum, minimum ) describing the distributions for power ( Po ), Reverse Current ( IR ) and Forward Voltage ( VF ), derived by sampling at the time these chips were manufactured. Taking advantage of these data, the team recreates the distribution of the chips per lot, and superimposes these distributions on the test program parameters. This way, the team can predict if the lot of chips has the tendency to exceed the VF2 test program limits. To do this, we need to transform x to Z and utilize Z to estimate the quantity of chips that will have VF reading less than or equal the VF2 test limit. This quantity is actually the acceptance region, quantity ( 1 - α ). To transform x to Z, x assumes the value of VF2 test limit.

Data and Formula
Chip Lot Data
Lot NumberMeanStd. DeviationQuantity Used
D8273.360.042912
B0263.240.035351
A0133.290.021337


Formula for Transforming x to z
Z = ( x - μ ) / σ

Calculated Values
Lot Numberz( 1 - α )αExpected Rejection Quantity
Under VF2
D8271.00 0.84130.1587 462 devices
B0265.330.9998 0.00021 device, equivalent to 0
A013 5.50 0.9998 0.0002 1 device, equivalent to 0


Plot

Reliability of the Method
The experiment assumes that the VF distribution of the chip lot under test is normal. If this assumption holds true, the result is accurate as what lot D827 manifested. But if the distribution of the lot is skewed, the results are way off the actual quantity of rejects, but indicative enough to flag the lot for possible VF2 occurrence.
Lot NumberEstimated QtyActual Quantity
D827462476
A913310213
C0971926203


References
[1] Walpole, Ronald and Myers, Raymond. Probability and Statistics for Engineers and Scientists, 3rd Edition. New York : Macmillan Publishing Company, 1978.

[2] Hoffa, David and Laux, Chad. "Gauge R&R: An Effective  Methodology for Determining the Adequacy of a New Measurement System for  Micron-level Metrology." http://atmae.org/jit/Articles/hoffa101707.pdf.